(China (Mainland))
Product Summary
The CY2304SI-2T is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The CY2304SI-2T has two banks of two outputs each. The CY2304SI-2T PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw.
Parametrics
CY2304SI-2T absolute maximum ratings: (1)Supply Voltage to Ground Potential:–0.5V to +7.0V; (2)DC Input Voltage (Except Ref):–0.5V to VDD + 0.5V; (3)DC Input Voltage REF:–0.5 to 7V; (4)Storage Temperature:–65 to +150℃; (5)Junction Temperature: 150℃; (6)Static Discharge Voltage: > 2000V.
Features
CY2304SI-2T features: (1)Zero input-output propagation delay, adjustable by capacitive load on FBK input; (2)Multiple configurations—see Available Configurations table; (3)Multiple low-skew outputs; (4)10-MHz to 133-MHz operating range; (5)90 ps typical peak cycle-to-cycle jitter at 15pF, 66MHz; (6)Space-saving 8-pin 150-mil SOIC package; (7)3.3V operation; (8)Industrial temperature available.
Diagrams
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 CY2300 |
Other |
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Data Sheet |
Negotiable |
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CY2300SXC |
Cypress Semiconductor |
Phase Locked Loops (PLL) 3.3VZDB COM |
Data Sheet |
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CY2300SXCT |
Cypress Semiconductor |
Phase Locked Loops (PLL) 3.3VZDB COM |
Data Sheet |
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CY2302 |
Other |
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Data Sheet |
Negotiable |
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CY23020-1 |
Other |
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Data Sheet |
Negotiable |
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CY23020LFI-3 |
Cypress Semiconductor |
Phase Locked Loops (PLL) 400MHz IND Zero Delay Buffer |
Data Sheet |
Negotiable |
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