LM3S6965IQC50A2

M3 based controller, 256K, 100-LQFP

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Price:: US $0.95~1.23 / piece [Get Latest Price]

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	US $0.95~1.23

PartNumber:: LM3S6965IQC50A2

Brand:: Texas Instruments - TI | Pack: DIP | D/C: 11+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-01-13

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Part Number:LM3S6965IQC50A2
US $0.95 - 1.23
A50L-0001-0175

US $100.00 - 100.00 / Piece
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IRFP260N

US $1.30 - 4.20 / Piece
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Product Summary

The LM3S6965IQC50A2 is a M3 based controller. It brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S6965IQC50A2 is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security.

Parametrics

LM3S6965IQC50A2 absolute maximum ratings: (1)VESDHBM:2.0 kV; (2)VESDCDM: 1.0 kV; (3)VESDMM: 100 V; (4)O supply voltage (VDD) VDD: 0 to 4 V; (5)Core supply voltage (VDD25) VDD25: 0 to 3 V; (6)Analog supply voltage (VDDA) VDDA: 0 to 4 V; (7)Battery supply voltage (VBAT) VBAT: 0 to 4 V; (8)Ethernet PHY supply voltage (VCCPHY) VCCPHY: 0 to 4 V; (9)Input voltage VIN: -0.3 to 5.5 V; (10)Maximum current per output pins I : 25 mA max.

Features

LM3S6965IQC50A2 features: (1)32-bit ARM Cortex M3 v7M architecture optimized for small-footprint embedded applications; (2)System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism; (3)Thumb compatible Thumb-2-only instruction set processor core for high code density 50-MHz operation; (4)Hardware-division and single-cycle-multiplication; (5)Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling; (6)38 interrupts with eight priority levels; (7)Memory protection unit (MPU), providing a privileged mode for protected operating system functionality; (8)Unaligned data access, enabling data to be efficiently packed into memory; (9)Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control.